129 lines
2.8 KiB
C
129 lines
2.8 KiB
C
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#ifndef __NFC_CHIPS_RC522_INTERNAL_H__
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#define __NFC_CHIPS_RC522_INTERNAL_H__
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#define FIFO_SIZE 64
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typedef enum {
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RC522_UNKNOWN = 0x00,
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FM17522 = 0x88,
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MFRC522_V1 = 0x91,
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MFRC522_V2 = 0x92
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} rc522_type;
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typedef enum {
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CMD_IDLE = 0x0,
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CMD_MEM = 0x1,
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CMD_GENRANDOMID = 0x2,
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CMD_CALCCRC = 0x3,
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CMD_TRANSMIT = 0x4,
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CMD_NOCMDCHANGE = 0x7,
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CMD_RECEIVE = 0x8,
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CMD_TRANSCEIVE = 0xC,
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CMD_MFAUTHENT = 0xE,
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CMD_SOFTRESET = 0xF
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} rc522_cmd;
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#define REG_CommandReg 0x01
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#define REG_CommandReg_RcvOff (1 << 5)
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#define REG_CommandReg_PowerDown (1 << 4)
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#define REG_CommandReg_Command_MASK 0x0F
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#define REG_ComlEnReg 0x02
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#define REG_DivlEnReg 0x03
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#define REG_ComIrqReg 0x04
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#define REG_DivIrqReg 0x05
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#define REG_DivIrqReg_MfinActIRq (1 << 4)
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#define REG_DivIrqReg_CRCIRq (1 << 2)
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#define REG_ErrorReg 0x06
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#define REG_Status1Reg 0x07
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#define REG_Status2Reg 0x08
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#define REG_Status2Reg_MFCrypto1On (1 << 3)
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#define REG_FIFODataReg 0x09
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#define REG_FIFOLevelReg 0x0A
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#define REG_FIFOLevelReg_FlushBuffer (1 << 7)
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#define REG_WaterLevelReg 0x0B
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#define REG_ControlReg 0x0C
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#define REG_BitFramingReg 0x0D
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#define REG_CollReg 0x0E
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#define REG_ModeReg 0x11
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#define REG_TxModeReg 0x12
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#define REG_TxModeReg_TxCRCEn (1 << 7)
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#define REG_TxModeReg_TxSpeed_106k (0 << 4)
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#define REG_TxModeReg_TxSpeed_212k (1 << 4)
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#define REG_TxModeReg_TxSpeed_424k (2 << 4)
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#define REG_TxModeReg_TxSpeed_847k (3 << 4)
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#define REG_TxModeReg_TxSpeed_MASK (7 << 4)
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#define REG_RxModeReg 0x13
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#define REG_RxModeReg_RxCRCEn (1 << 7)
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#define REG_RxModeReg_RxSpeed_106k (0 << 4)
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#define REG_RxModeReg_RxSpeed_212k (1 << 4)
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#define REG_RxModeReg_RxSpeed_424k (2 << 4)
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#define REG_RxModeReg_RxSpeed_847k (3 << 4)
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#define REG_RxModeReg_RxSpeed_MASK (7 << 4)
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#define REG_TxControlReg 0x14
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#define REG_TxControlReg_Tx2RFEn (1 << 1)
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#define REG_TxControlReg_Tx1RFEn (1 << 0)
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#define REG_TxASKReg 0x15
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#define REG_TxSelReg 0x16
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#define REG_RxSelReg 0x17
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#define REG_RxThresholdReg 0x18
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#define REG_DemodReg 0x19
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#define REG_MfTxReg 0x1C
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#define REG_MfRxReg 0x1D
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#define REG_MfRxReg_ParityDisable (1 << 4)
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#define REG_SerialSpeedReg 0x1F
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#define REG_CRCResultReg 0x21
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#define REG_ModWidthReg 0x24
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#define REG_RFCfgReg 0x26
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#define REG_GsNReg 0x27
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#define REG_CWGsPReg 0x28
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#define REG_ModGsPReg 0x29
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#define REG_TModeReg 0x2A
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#define REG_TPrescalerReg 0x2B
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#define REG_TReloadReg 0x2C
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#define REG_TCounterValReg 0x2E
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#define REG_TestSel1Reg 0x31
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#define REG_TestSel2Reg 0x32
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#define REG_TestPinEnReg 0x33
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#define REG_TestPinValueReg 0x34
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#define REG_TestBusReg 0x35
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#define REG_AutoTestReg 0x36
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#define REG_AutoTestReg_SelfTest_Disabled (0x0 << 0)
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#define REG_AutoTestReg_SelfTest_Enabled (0x9 << 0)
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#define REG_AutoTestReg_SelfTest_MASK (0xF << 0)
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#define REG_VersionReg 0x37
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#define REG_AnalogTestReg 0x38
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#define REG_TestDAC1Reg 0x39
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#define REG_TestDAC2Reg 0x3A
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#define REG_TestADCReg 0x3B
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#endif
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